1. Technical Field
The present disclosure relates to the field of clock and data recovery circuits. The present disclosure relates more particularly to the field of oversampling clock and data recovery circuits.
2. Description of the Related Art
In embedded clock serial link receivers, data and clock have to be recovered from the incoming NRZ bit stream without the aid of any additional clock input from the transmitter side. The challenge is to recover the data bits in the presence of jitter, keeping the rate of errors within a target bit error rate (BER) limit, and to provide a clock output to the next higher communication layer on the receiver side that follows the transmitter frequency deviations.
Clock and data recovery circuits (CDR) are used for this purpose. The performance figures of merit of any CDR are its lock time, jitter tolerance at targeted BER, and tolerable frequency difference between TX and RX.
One class of CDR circuits is based on oversampling the incoming bit stream and processing the samples with algorithms (e.g., phase picking/tallying) to determine the sample most likely to represent the data sent by the transmitter. In an oversampling CDR, a phase locked loop generates multiple phases of a bit rate clock for taking multiple samples of each incoming bit. These samples are collected and resynchronized to a divided version of the bit rate clock and then processed according to an algorithm to choose the most appropriate sample as the recovered data. The recovered data and the divided clock are the outputs of the CDR. However, the frequency of the clock on the receiver side may not exactly mirror the deviations in the frequency of the transmitter clock. To alleviate this problem an appropriately sized first in first out (FIFO) elasticity buffer is included inside the CDR to absorb the frequency difference between TX and RX over the maximum burst length targeted by the serial link protocol. The larger the FIFO, the larger the max burst size can be. However, as the FIFO becomes large, the chip area consumed by the FIFO increases and hence the area of CDR also increases.